BENDIX BENDIX 7129 Uživatelský manuál stáhnout pdf (Strana 1)

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

192-Bit, 360 MHz True-Color

Video DAC with Onboard PLL

ADV7129

FEATURES

192-Bit Pixel Port Allows 2048 3 2048 3 24 Screen

Resolution

360 MHz, 24-Bit True-Color Operation

Triple 8-Bit D/A Converters

8:1 Multiplexing

Onboard PLL

RS-343A/RS-170 Compatible Analog Outputs

TTL Compatible Digital Inputs

Internal Voltage Reference

Standard 8-Bit MPU I/O Interface

DAC-DAC Matching: Typ 2%, Adjustable to 0.02%

+5 V CMOS Monolithic Construction

304-Pin PQFP Package

APPLICATIONS

Ultrahigh Resolution Color Graphics

Image Processing

Drives 24-Bit Color 2K 3 2K Monitors

GENERAL DESCRIPTION

The ADV7129 is a complete analog output, video DAC on a single

CMOS (ADV®) monolithic chip. The part is specifically designed

for use in the highest resolution graphics and imaging systems.

The ultimate level of integration, comprised of 360 MHz triple

8-bit DACs, a programmable pixel port, an internal voltage refer-

ence and an onboard PLL, makes the ADV7129 the only choice

for the very highest level of performance and functionality.

The device consists of three high speed, 8-bit, video D/A con-

verters (RGB). An onboard phase locked loop clock generator

is provided to provide high speed operation without requiring

high speed external crystal or clock circuitry.

The part is fully controlled through the MPU port by the on-

board command registers. This MPU port may be updated at

any time without causing sparkle effects on the screen.

ADV is a registered trademark of Analog Devices, Inc.

(continued on page 10)

FUNCTIONAL BLOCK DIAGRAM

ODD/EVEN

PIXEL

DATA

(RED,

GREEN,

BLUE)

LOADIN

LOADOUT

LPF

REF

IOR

MPU PORT

D7–D0CE R/W C0 C1

ADV7129

GND

CONTROL

REGISTERS

IOR

IOG

IOB

RCOMP

GCOMP

BCOMP

RSET

GSET

BSET

BLANK

HSYNC

VSYNC

CSYNC

VOLTAGE

REFERENCE

SENSE/SYNCOUT

CLOCK

CONTROL

PLL

INT PIXEL

CLOCK

BLANK

AND SYNC

LOGIC

GREEN

DAC

BLUE

DAC

RED

DAC

MUX

8:1

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700 World Wide Web Site: http://www.analog.com

Fax: 617/326-8703 © Analog Devices, Inc., 1996

ADV is a registered trademark of Analog Devices, Inc..

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Shrnutí obsahu

Strany 1 - Video DAC with Onboard PLL

REV. 0Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsu

Strany 2 - ADV7129–SPECIFICATIONS

ADV7129–10–REV. 0SENSEIf any one or more of the analog outputs, IOG, IOR and IOB,exceed the internal voltage reference level (due to absence ofCRT), S

Strany 3 - TIMING SPECIFICATIONS

ADV7129–11–REV. 0REGISTER PROGRAMMINGThe following section describes each register, including AddressRegister and each of the Control Registers in ter

Strany 4 - OUTPUT PIPELINE

ADV7129–12–REV. 0COMMAND REGISTER 2 (CR2)(Address Register (A10–A0) = 411H)This register contains a number of control bits as shown in thediagram. CR

Strany 5 - WARNING!

ADV7129–13–REV. 0DIGITAL-TO-ANALOG CONVERTERS (DACS)AND VIDEO OUTPUTSThe ADV7129 contains three high speed video DACs. TheDAC outputs are represented

Strany 6 - PIN ASSIGNMENTS

ADV7129–14–REV. 0Table I. Video Output Truth Table (RSET = 398V, RLOAD = 37.5V)O/P with Sync O/P with Sync DACDescription Enabled (mA) Disabled (mA) S

Strany 7 - *No Connect

ADV7129–15–REV. 0APPENDIX IBOARD DESIGN AND LAYOUT CONSIDERATIONSThe ADV7129 is a highly integrated circuit containing bothprecision analog and high s

Strany 8 - Figure 5

ADV7129–16–REV. 0PIXELDATA192RBIASGBIASBBIASRCOMPGCOMPBCOMPIORIORIOGIOGIOBIOBRRSETGRSETBRSET+5V(VAA)ANALOG POWER PLANE10µF33µFFERRITE BEAD+5V(BOARD SU

Strany 9

ADV7129–17–REV. 0APPENDIX IITHERMAL AND ENVIRONMENTAL CONSIDERATIONSThe ADV7129 is a very highly integrated monolithic silicondevice. This high level

Strany 10

ADV7129–18–REV. 0OUTLINE DIMENSIONSDimensions shown in inches and (mm).304-Lead Plastic Quad Flatpack(S-304)SEATINGPLANE0.167 (4.23)NOM0.150 (3.80) NO

Strany 11 - Figure 7. Command Register 1

–19–

Strany 12 - Figure 9. Gain Error Register

ADV7129–SPECIFICATIONSAll Versions Conditions1Min Typ Max UnitsSTATIC PERFORMANCE3Resolution (Each DAC) 8 BitsAccuracy (Each DAC)Integral Nonlinearity

Strany 13 - AND VIDEO OUTPUTS

PRINTED IN U.S.A.C2215–6–10/96–20–

Strany 14

ADV7129–3–REV. 0TIMING SPECIFICATIONSParameter Conditions Min Typ Max UnitsCLOCK CONTROL & PIXEL PORT4LOADIN Clocking Rate, fLCLK10 45 MHzLOADIN

Strany 15

ADV7129–4–REV. 0AN ...HNAN+1 ...HN+1AN+2 ...HN+2DIGITAL INPUT TO ANALOG OUTPUT PIPELINEAN+2 ... HN+2AN+1 ... HN+1AN ... HNAN–1 ... HN–1LOADOUTLOADINP

Strany 16

ADV7129–5–REV. 0ABSOLUTE MAXIMUM RATINGS1VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VVoltage on Any Digita

Strany 17 - Package Characteristics

ADV7129–6–REV. 0PIN ASSIGNMENTSPin No. Mnemonic Pin No. Mnemonic Pin No. Mnemonic Pin No. Mnemonic1 GND 41 G4C81 GND 121 B4E2 GND 42 G4B82 GND 122 B4D

Strany 18 - OUTLINE DIMENSIONS

ADV7129–7–REV. 0Pin No. Mnemonic Pin No. Mnemonic Pin No. Mnemonic Pin No. Mnemonic161 B1A197 RBIAS233 GND 269 LOADOUT162 B0H198 SENSE/SYNCOUT 234 GND

Strany 19

ADV7129–8–REV. 0PIN DESCRIPTIONMnemonic FunctionR7–R0[A . . . H] Red Pixel Port Inputs (TTL Compatible Inputs). Eight sets of eight bits latched on th

Strany 20 - C2215–6–10/96

ADV7129–9–REV. 0Mnemonic FunctionIOR, IOG, IOB Red, Green & Blue Current Outputs (High Impedance Current Sources). These RGB video outputs aresp